Test Pattern Simulation
Posted: Mon Feb 22, 2016 7:49 pm
Hello there,
can any one tell me about the mismatches occurred during zero delay simulation after pattern generation in ATPG. As I know there is one mismatch due to pin constraints / cut points. Is there any other mismatch ?
can any one tell me about the mismatches occurred during zero delay simulation after pattern generation in ATPG. As I know there is one mismatch due to pin constraints / cut points. Is there any other mismatch ?