Search found 2 matches
- Wed Jan 13, 2016 7:34 am
- Forum: Digital Design
- Topic: Design flow
- Replies: 0
- Views: 14093
Design flow
What is wire load model and parasitic extraction?
- Wed Jan 13, 2016 7:32 am
- Forum: Digital Design
- Topic: Behavioral synthesis
- Replies: 0
- Views: 14099
Behavioral synthesis
Q1. Why resource sharing at same clock cycle in logic synthesis is possible and why not in behavioral synthesis?
Q2. Why logic synthesis do not infer combination and multi cycle paths??
Q2. Why logic synthesis do not infer combination and multi cycle paths??